1. Field of the Invention
The present invention relates to microprocessors and is a technique for making effective use of redundant areas and unused areas that are present within instructions.
2. Description of the Prior Art
In recent years, increases in processing capability and processing speed of appliances using embedded microprocessors have led to an increasing demand for microprocessors (hereinafter simply referred to as "processors") that can execute programs with high code efficiency. This means that it is preferable for there to be no redundant areas or unused areas in the instructions which compose a program.
In particular, when using fixed length instructions, such as VLIW (Very Long Instruction Words), there are cases when it is necessary to insert redundant codes, such as no-operation codes ("nop" codes), into instructions. VLIW are composed of a plurality of operation fields, with each operation field specifying an operation which corresponds to one of a plurality of operation units provided within a processor. Due to interdependencies between operations, however, it is not always possible to process a plurality of operations using parallel processing.
One conventional method of avoiding the decreases in code efficiency that accompany the insertion of "nop" codes is the VLIW-type computer system disclosed by Japanese Laid-Open Patent Application H08-161169.
FIG. 1 shows the instruction format used in the above technique.
As shown in FIG. 1, when a "nop" code needs to be inserted into operation field#2, this technique inserts a constant that is to be used by a different operation in place of the "nop" code into operation field #2 and inserts instruction validation information into one part of operation field #1 to show that the constant has been inserted. When executing this instruction, a processor first refers to the instruction validation information and so determines that only a constant is present in operation field #2. The processor then uses this constant as the operand of an operation. In this way, the existence of redundant areas within instructions due to the insertion of "nop" codes can be avoided.
The above technique, however, has a drawback in that the size of the constants that can be inserted into the redundant areas is limited.
As one example, when it is necessary to insert a "nop" code into a 32-bit operation field, it is not possible to insert any part of a 64-bit constant. Similarly, when there is an unused 8-bit area in a fixed 32-bit instruction, it is only possible to use the unused area when inserting a constant which is 8 bits long or shorter. In this case, it is not possible to insert an absolute address which is expressed using 32 bits.
While the above technique may be effective when there is a relatively large redundant area in an instruction, when instructions have a relatively short length, such as 32 bits, any redundant area in the instructions will naturally be short, preventing the insertion of constants into a large number of redundant areas when using the above technique. This constitutes a major problem.
As a potential solution to the above problem, a processor could conceivably be provided with a specialized register ("constant register") for storing constants. However, a processor provided with such a register would suffer from increases in processing time for context switching during multitasking. To perform multiple tasks by switching the processing according to time division, the processor needs to operate as follows. The processor needs to switch to the operating system during the execution of a task, to save the information ("context") that is required for the recommencement of the execution of the task into a saving area, such as memory, and then to restore the context of the next task to be executed. This procedure is called "context switching", and has to be performed with a high frequency. When a value stored in a constant register is also included in a context, this adds to the processing time required when performing task switching.